Principal, MTS, DRAM Systems Architect
Core
Design, develop, optimize, and verify high-speed IO and clocking circuits for critical DRAM memory products, focusing on equalization, bandwidth extension, and timing analysis.
Role type
Principal/Member of Technical Staff (MTS) IO/Clock Design Engineer
Builds
High-speed IP circuits for Micron's DRAM memory products
Domain
Semiconductor / Memory / High-speed circuit design
Required skills
High-speed IO interface design, Timing and clocking circuit design, Circuit simulation and modeling, Full-chip timing analysis, Jitter and duty cycle distortion analysis, Layout practices for high-speed circuits
Preferred skills
DRAM circuit design, Channel modeling and characterization, Transceiver noise and timing budget analysis, Equalization techniques, SI knowledge, Device physics, CMOS processing techniques, AI/ML usage, Scripting (PERL/Python), Agentic AI, Mentoring
Technologies
EDA tools, AI/ML frameworks, Scripting languages (PERL, Python)
Responsibilities
Innovate, design, optimize and verify high-speed IO and clocking circuits used in new DRAM products. Apply robust high-speed circuit design techniques to enhance critical performance evaluation of the IO data path and clock path. Develop accurate modeling, analysis and simulation methodology to capture key circuit performance metrics. Work with Product Engineering and SI team to compare silicon performance with simulation results. Collaborate with process integration and transistor modeling teams on next groundbreaking process node. Work with the internal data science team and EDA vendors to leverage and improve AI-assisted design flow and circuits optimization.
Seniority
Principal, hands-on IC with mentorship
