Principal Analog and Reliability Verification Engineer
Core
Define and drive DRAM analog verification strategy, develop scalable verification solutions, and improve coverage and efficiency for next-generation DRAM products.
Role type
Principal Analog and Reliability Verification Engineer
Builds
Next-generation DRAM products
Domain
Semiconductor / Memory / Analog Verification
Deliverable
production ML models
Required skills
Analog verification, Python (advanced), Gate-level analog simulation, VLSI circuit design, AI/LLM application, Object-oriented design
Preferred skills
DRAM circuit design, Reliability fundamentals (BTI, HCI, EM, TDDB), Digital verification (SystemVerilog, UVM)
Technologies
Python, LLMs, Agentic AI tools, SystemVerilog, UVM
Responsibilities
Define and drive DRAM analog verification strategy including AI-enabled methodologies; Partner with design teams to standardize verification methodologies; Develop and maintain Python-based analog and reliability verification test benches; Provide technical leadership by mentoring engineers and driving innovation.
Seniority
Principal, hands-on IC with mentorship