Senior Staff Engineer, Hardware & Silicon Validation
Core
Deliver high bandwidth over long distances by performing analog validations on amplifiers, silicon photonics, and coherent digital signal programming for PCIe/Ethernet PHYs.
Role type
Senior Staff IC hardware validation engineer (high-speed SERDES/PHY)
Builds
PCIe/Ethernet Physical & PCS layer hardware and firmware functionality for Marvell's in-house IP
Domain
Semiconductor / High-speed data infrastructure (PCIe, Ethernet, Silicon Photonics)
Required skills
High-speed SERDES, PCIe protocols, equalization techniques, lab-based silicon bring-up, test equipment operation (Scope, BERT, Network analyzer), validation-automation development, data analysis with scripting (Python, Matlab)
Preferred skills
SAS/SATA SERDES, physical and protocol levels (PIPE I/F, PCS, MAC), board design/schematics reading, SERDES modeling techniques
Responsibilities
Define, document, execute, and report overall PHY validation/test plans; Perform high-speed signal validation and analysis (Eye diagram/Jitter/BER); Troubleshoot failing tests using diagnostics and hardware analyzers; Lead collaborative technical discussions to drive resolution; Work with cross-functional teams and external vendors to debug post-silicon and customer issues
Seniority
Senior Staff, hands-on IC
