CareerPlan

Co-Packaged Optics Packaging Process Development Engineer

Santa Clara, CA, USFull-time$141k–$211k2026-11-05 → 2026-11-10
Citizens or permanent residents only

Core

Drive assembly process technology development for 2.5D/3D Co-Packaged Optics (CoW) and AI products from concept to high volume manufacturing, ensuring design for manufacturing, reliability, and cost.

Role type

Senior IC process development engineer (semiconductor packaging)

Builds

2.5D/3D CoW assembly solutions, high density interconnects with TSVs, and advanced package solutions for AI and data infrastructure.

Domain

Semiconductor manufacturing, advanced packaging, photonics integration

Required skills

wafer process development, 2.5D/3D CoW assembly, chemistry development with consumable suppliers, physics of failures analysis, NPI management, project management, cross-functional team leadership, executive-level communication, problem-solving, analytical ability

Preferred skills

photonics packaging experience, component & system level reliability testing

Technologies

TSV, 2.5D/3D packaging, OSAT processes, foundry process nodes

Responsibilities

Manage qualification of packages with sensitivity to physics of failures for high thermo-mechanical reliability; Drive ideation and innovation of advanced package solutions and specifications with vendors; Identify and mitigate risk to new technologies used in product integration; Ensure factory readiness through maturing product during the NPI phase; Work with cross-functional packaging teams and lead process development at foundry along with 2.5D/3D CoW process development.

Seniority

Senior, hands-on IC