Design for Test Intern, BS - Summer 2027
Core
Design and implement Design-for-Test (DFT) designs and reference flows for System-on-Chip (SoC) architectures to ensure successful delivery to end clients.
Role type
Entry-level Design-for-Test (DFT) intern
Builds
DFT designs and reference flows for SoC
Domain
Semiconductor / Hardware Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
CAD tools/flow, Linux, TCL, Python/Perl, SoC design flow, DFT practices, ICL/PDL, SV/UVM
Preferred skills
Linux/Unix/BSD Internals, multi-threaded systems, At-Speed Test, Built-in Self-Test (BIST), Automated Test Pattern Generation (ATPG), IEEE1149.6, IEEE1687
Technologies
Linux, TCL, Python, Perl, ICL, PDL, SV, UVM
Responsibilities
Understand design requirements and customer specifications, run defined CAD tools/flow, design and develop SoC using scripting languages, analyze and debug DFT features, collaborate on design flow fixes, assist in design verification efforts
Seniority
Intern
