Analog Design Intern, MS - Summer 2027
Core
Design and verify test chip experiments using Verilog simulation and develop automation scripts for hardware characterization and data analysis.
Role type
MS-level intern analog/digital design engineer (test chip development)
Builds
Test chips for hardware validation of custom SRAM, logic, I/O, and security circuits
Domain
Semiconductor hardware design and validation
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Verilog simulation, digital logic circuits, memory architectures, I/O circuits, semiconductor device physics, Linux/Unix environments, Perl scripting, Python scripting, Tcl scripting
Preferred skills
Cross-functional team collaboration, hardware debug, diagnostics, measurement data collection
Technologies
Verilog, Perl, Python, Tcl, Linux/Unix
Responsibilities
Design and verify test chip experiments using Verilog simulation; Develop, generate, simulate, and debug Verilog-based test patterns; Create software tools and automation scripts for design support and data processing; Analyze, summarize, document, and present characterization and validation results
Seniority
Intern (MS student)
