Design Verification Intern, MS - Summer 2027
Core
Design Verification Intern creating simulation environments and automated tests for next-generation cloud, AI, storage, and networking chips.
Role type
Intern, Design Verification Engineer
Builds
Simulation environments and automated testbenches for ASIC/SOC designs
Domain
Semiconductor / Hardware Design / Verification
Required skills
Verilog, VLSI, VHDL, UVM, Python, C, C++, Perl, Java, RTL integration, debugging hardware/software interactions
Preferred skills
Computer architecture, logic design, processor design, memory system design, analog IC design, signal processing
Technologies
Synopsys, Cadence, Mentor
Responsibilities
Create powerful simulation environments mimicking real-world conditions; Develop smart, automated tests to find hidden flaws and troubleshoot failed simulations; Analyze test coverage results & metrics; Collaborate with chip architects and designers to solve complex problems
Seniority
Intern
