Design Verification Intern, MS - Summer 2027
Core
Intern role focused on creating simulation environments and automated tests to verify chip designs, finding flaws, and analyzing test coverage.
Role type
Design Verification Intern
Builds
Simulation environments and automated testbenches for pre-silicon emulation and ASIC design verification
Domain
Semiconductor / Chip Design / Data Infrastructure
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Verilog, VLSI, VHDL, UVM, Python, C, C++, Perl, Java, RTL integration, debugging hardware/software interactions
Preferred skills
Experience with Synopsys, Cadence, or Mentor tools
Technologies
Synopsys, Cadence, Mentor
Responsibilities
Create simulation environments mimicking real-world conditions, develop automated tests to break designs and find hidden flaws, analyze test coverage results and metrics, collaborate with chip architects and designers to solve complex problems
Seniority
Intern
