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Ph.D. Intern - Analog, Mixed Signal & Circuit Design

Santa Clara, CA, US💼 Internship💰 $79,040–$158,080🗓 2026-09-04 → 2026-09-27

Core

Design analog and mixed-signal circuit blocks for production-grade IP and research-stage silicon in advanced CMOS processes, supporting hyperscaler AI infrastructure.

Role type

Ph.D. Analog Design Intern (IC)

Builds

High-speed SerDes, Silicon Photonics, ADC/DAC, PLLs, and clock distribution networks

Domain

Semiconductor / Analog & Mixed-Signal Circuit Design

Deliverable

production ML models | product features

Required skills

Transistor-level circuit design, Device physics, Noise analysis, Linearity analysis, Stability analysis, Low-power techniques, Schematic design, Simulation and verification, Layout coordination

Preferred skills

FinFET process node experience (7nm/5nm/3nm), High-speed serial link architectures, Optical transceiver circuits, Layout-aware design, Behavioral modeling (Verilog-A)

Technologies

Cadence Virtuoso, Spectre, MATLAB, Python

Responsibilities

Design, simulate, and verify analog/mixed-signal blocks across the full design flow; Collaborate with layout engineers for implementation and iteration; Present research framing and design results to the engineering team; Participate in structured analog design curriculum

Seniority

Intern, Research-focused IC

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