Senior Staff Design Verification Engineer – PCIE/CXL Sub-System
Core
End-to-end verification of PCIe (Gen6/Gen7) and CXL (3.0/4.0) subsystems for Marvell's custom chips serving hyperscale cloud, AI, and data center customers.
Role type
Senior Staff Design Verification Engineer (PCIe/CXL)
Builds
Production-ready IP subsystems for PCIe/CXL controllers and fabric-level subsystems
Domain
Semiconductor / High-speed memory interfaces (PCIe, CXL)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
System Verilog, UVM methodology, PCIe protocol architecture, CXL protocol architecture, ASIC/SoC verification, digital design fundamentals, simulation tools, waveform debugging, coverage closure
Preferred skills
Assertion-based verification (SVA), performance modeling, traffic generation, emulation platforms (Palladium, Veloce), low-power verification (UPF), scripting (Python/Perl/Shell)
Technologies
System Verilog, UVM, Python, Shell, Palladium, Veloce
Responsibilities
Own end-to-end verification of PCIe and CXL subsystems from test planning through signoff; Architect and develop scalable UVM/System Verilog testbenches; Validate CXL.io, CXL.cache, and CXL.mem protocols including coherency; Debug complex failures using waveforms and protocol analyzers; Drive functional, code, and assertion coverage closure; Develop automation for regression management and coverage reporting.
Seniority
Senior Staff, hands-on IC
