Sr Staff Digital Design Engineer
Core
Design, develop, implement, verify, and document micro-architecture and RTL for complex power management integrated circuits within custom SoC initiatives.
Role type
Sr Staff Digital Design Engineer (ASIC/SoC)
Builds
High-quality customer silicon for advanced AI, XPU, and XPU-Attach programs
Domain
Semiconductor / Custom Compute / ASIC Design
Deliverable
production ML models | product features
Required skills
SystemVerilog RTL coding, high-speed multi-clock domain design, SoC architecture (AXI, DDR, Ethernet, PCIe), micro-architecture of custom/ASIC products, static-timing closure, formal verification, SVA assertions, Python/Perl/Tcl/UNIX scripting
Preferred skills
Creative problem solving, technical leadership, process efficiency in ASIC design flow
Technologies
SystemVerilog, Python, Perl, Tcl, UNIX shell, AXI, DDR, Ethernet, PCIe
Responsibilities
Design and verify micro-architecture and RTL for power management ICs; collaborate with system architects on industrial quality implementations; manage full design cycle from specification to silicon bring-up; create block micro-architecture and register specs; conduct cross-functional design reviews; improve design and verification methodologies
Seniority
Sr Staff, hands-on IC with technical leadership
