Principal Digital Design Engineer
Core
Design, develop, implement, verify, and document micro-architecture and RTL for complex power management integrated circuits within advanced AI and XPU programs.
Role type
Principal Digital Design Engineer (ASIC/SoC)
Builds
Custom SoC initiatives for advanced AI, XPU, and XPU-Attach programs
Domain
Semiconductor / ASIC Design / High-Speed Interfaces
Deliverable
production ML models | product features
Required skills
SystemVerilog RTL coding, high-speed multi-clock domain design, PCIe/CXL protocols, SoC architecture (AXI, DDR, Ethernet), micro-architecture of custom/ASIC products, RTL design, synthesis, static-timing closure, formal verification, gate-level simulation, block-level functional verification
Preferred skills
High-speed (>1 GHz) embedded processor SOC design, implementation/timing closure for high-speed design, scripting languages (Python, Perl, Tcl, UNIX shell), creative problem solving
Technologies
SystemVerilog, PCIe, CXL, AXI, DDR, Ethernet, Python, Perl, Tcl, UNIX shell
Responsibilities
Design and verify micro-architecture and RTL for power management ICs; Collaborate with system architects on industrial quality implementations; Define design strategy and build a world-class team in San Diego; Mentor digital design engineers; Create block micro-architecture and register specifications; Evaluate and improve design and verification methodologies
Seniority
Principal, technical leadership & team building
