Sr Principal Digital Design Engineer
Core
Lead the design, development, and verification of micro-architecture and RTL for complex power management integrated circuits within custom SoC initiatives for advanced AI and XPU programs.
Role type
Sr Principal Digital Design Engineer (Power Management & Custom SoC)
Builds
High-quality customer silicon for advanced AI, XPU, and XPU-Attach programs
Domain
Semiconductor / ASIC Design / Power Management
Deliverable
production ML models | product features | infrastructure
Required skills
SystemVerilog RTL coding, high-speed multi-clock domain design, PCIe/CXL protocols, micro-architecture of custom/ASIC products, RTL design, synthesis, static-timing closure, formal verification, gate-level simulation, block-level functional verification
Preferred skills
High-speed (>1 GHz) embedded processor SOC design, scripting languages (Python, Perl, Tcl, UNIX shell), creative problem solving, technical leadership
Technologies
SystemVerilog, PCIe, CXL, AXI, DDR, Ethernet, Python, Perl, Tcl, UNIX shell
Responsibilities
Design, develop, implement, verify, and document micro-architecture and RTL; Work with system and chip architects to design industrial quality implementations; Participate in the full design development cycle from documentation to silicon bring-up; Produce comprehensive block micro-architecture and register specs; Schedule detailed reviews with cross-functional teams; Supervise or mentor other digital design engineers
Seniority
Sr Principal, hands-on IC with strategic leadership
