Distinguished Engineer - Digital Design
Core
Establishing a new design center in San Diego to deliver high-quality customer silicon for advanced AI, XPU, and XPU-Attach programs, shaping design strategy and building a world-class team from the ground up.
Role type
Distinguished Engineer - Digital Design (Technical Leadership)
Builds
Custom SoC initiatives for next-generation compute platforms (AI, XPU, XPU-Attach)
Domain
Semiconductor / ASIC Design / High-Performance Computing
Deliverable
production ML models | product features
Required skills
SystemVerilog RTL coding, high-speed multi-clock domain design, PCIe/CXL protocols, micro-architecture of complex custom/ASIC products, formal verification (SVA), static-timing closure, front-end design tools and methodologies
Preferred skills
High-speed (>1 GHz) embedded processor SOC design, scripting languages (Python, Perl, Tcl, UNIX shell), post-silicon debug environments
Technologies
SystemVerilog, SVA, Python, Perl, Tcl, UNIX shell, AXI, DDR, Ethernet, PCIe, CXL
Responsibilities
Shape micro-architecture and write specifications for chip designs; Implement designs using low-power RTL coding techniques; Collaborate with verification teams on test plans, coverage analysis, and full-chip simulation; Prepare and present design reviews; Work with physical design teams to aid implementation of functional blocks; Provide expert product support in post-silicon debug environments; Define culture, methodology, and technical DNA for the new San Diego design organization.
Seniority
Distinguished, strategic leadership & hands-on IC
