Sr Principal Digital Design Engineer
Core
Lead digital design architecture and RTL implementation for power management ICs including LED drivers, SiC drivers, smart-switches, and efuses.
Role type
Sr Principal Digital Design Engineer (SoC/ASIC)
Builds
Power management chips for consumer, industrial, and automotive applications
Domain
Semiconductor / Power Management / ASIC Design
Deliverable
production ML models | product features
Required skills
Digital design architecture, RTL design, low power design, synthesis, timing analysis, CDC, UPF, System Verilog, Verilog, TCL, Perl/Python/XML, micro-processor interconnects, peripheral integration
Preferred skills
Experience with SOCV, Emulation, FPGA, Failure Analysis, post-silicon validation
Technologies
Verilog, System Verilog, TCL, Perl, Python, XML, SOCV, FPGA
Responsibilities
Define and implement micro-architecture to RTL, support feature bring-up on pre-silicon platforms, own technical outcome of design and verification, lead customer and production issue resolution, support post-silicon validation
Seniority
Sr Principal, hands-on IC design & architecture