Senior Design Verification Engineer
Core
Ensure functional correctness, quality, safety, and security of configurable RISC-V CPU IP through simulation, formal verification, and AI-assisted methods.
Role type
Senior Design Verification Engineer (CPU/RISC-V)
Builds
RISC-V CPU IP for automotive, industrial, security, and edge-AI applications
Domain
Semiconductor / CPU Architecture / RISC-V
Deliverable
production ML models | product features
Required skills
SystemVerilog, UVM, formal verification, verification planning, metric-driven verification, coverage analysis, debugging, processor architecture concepts (pipelines, exceptions, interrupts, memory access)
Preferred skills
RISC-V architecture, ISO 26262, fault-oriented verification, security verification, AI-assisted engineering
Technologies
SystemVerilog, UVM, formal verification tools
Responsibilities
Define and execute verification plans for RISC-V CPU features and custom extensions; Develop reusable verification environments, assertions, checkers, and regression infrastructure; Verify ISA behavior, privilege modes, exceptions, interrupts, and memory interfaces; Combine simulation and formal techniques to address complex control logic; Apply metric-driven verification to support sign-off decisions; Debug complex failures and collaborate with architecture and integration teams; Execute requirements traceability and fault-oriented verification for safety/security certifications; Help define and evaluate AI-assisted verification methods.
Seniority
Senior, hands-on IC
