Staff Mixed-Signal Verification – Analog IP
Core
Develop and execute mixed-signal verification solutions for analog IP blocks integrated into digital-on-top SoC environments on the Treo platform.
Role type
Staff mixed-signal verification engineer (analog IP)
Builds
Scalable digital-on-top testbenches and verification environments for power and clock IP
Domain
Semiconductor IC design, mixed-signal verification, automotive/industrial power management
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM-based verification, behavioral modeling (Verilog-A/AMS or SystemVerilog real-number), regression analysis, root cause debugging, coverage-driven verification
Preferred skills
Power management/clocking architecture knowledge, assertion-based methodologies, automotive silicon reliability experience, automation/scripting
Technologies
SystemVerilog, UVM, Verilog-A, AMS, 65nm BCD technology
Responsibilities
Own mixed-signal verification for assigned analog IP blocks; Develop scalable testbenches with behavioral models of analog IP; Translate analog specs into verification plans and checkers; Execute regressions and drive debug across boundaries; Verify configuration and fault-handling interfaces; Mentor junior verification engineers
Seniority
Senior, hands-on IC
