Intern in Digital RTL design and automation
Core
Develop RTL for mix-signal state-of-the-art converters and Arithmetic Logic Units (ALU) using SystemVerilog/Verilog, and implement automation using IPXACT MESA flow.
Role type
Intern, Digital RTL Design and Automation
Builds
Mix-mode converters and ALUs for intelligent power and sensing technologies
Domain
Semiconductor / Analog and Digital IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, Verilog, RTL design, functional simulation, verification, debugging, digital IC design, computer architecture, low-power design, digital system integration
Preferred skills
IPXACT, Linux shell environment, FPGA prototyping flows
Technologies
SystemVerilog, Verilog, IPXACT MESA flow
Responsibilities
Develop and implement RTL modules, perform functional simulation and verification, participate in integration through automation, collaborate with cross-functional teams
Seniority
Intern
