Design Verification Engineering Intern - Bachelors
Core
Develop verification plans, test benches, and simulations for mixed-signal circuits to ensure pre-silicon verification success.
Role type
Design Verification Intern
Builds
Verification environments and test cases for mixed-signal and digital circuits
Domain
Semiconductor hardware design verification
Required skills
SystemVerilog, constrained-random stimulus, RTL verification, Gates+SDF timing analysis, regression tools scripting, mixed-signal circuit verification
Preferred skills
stakeholder relationship building, rapid system ramp-up, analytical problem-solving, team collaboration, project delivery management
Technologies
SystemVerilog, RTL, Gates+SDF, regression tools
Responsibilities
Develop detailed verification plans, create test benches and simulations, run coverage regressions, track verification status and issues, develop regression scripts, contribute to DV strategy improvements
Seniority
Intern
