Lead RTL Engineer ( Mixed-Signal IPs)
Core
Develop, integrate, and verify digital RTL blocks within mixed-signal subsystems (ADC/DAC, PLL/DLL, power management) for low-power wireless SoCs.
Role type
Senior IC RTL Design Engineer (Mixed-Signal)
Builds
Mixed-signal IP blocks and SoC top-level integration for smart home, industrial IoT, and smart cities applications.
Domain
Semiconductor / Mixed-Signal SoC Design
Deliverable
production ML models | product features
Required skills
Verilog/SystemVerilog, Synthesis, Static Verification (lint, CDC), Mixed-signal concepts (sampling, clocking, calibration), Digital protocols (SPI, I2C, APB, AXI), Python/TCL scripting
Preferred skills
AMS co-simulation tools (Cadence AMS Designer, Synopsys VCS AMS), AI-powered productivity tools
Technologies
Verilog, SystemVerilog, Python, TCL, Cadence AMS Designer, Synopsys VCS AMS
Responsibilities
Develop synthesizable RTL for mixed-signal interfaces; Collaborate with analog teams on interface specs; Perform behavioral modeling and co-verification; Execute design quality checks (lint, CDC, synthesis readiness); Integrate IPs into SoC top-level RTL; Drive coverage closure and debug digital-analog boundary issues.
Seniority
Senior, hands-on IC
