Principal Verification Engineer
Core
Ensure functional correctness, robustness, and quality of cutting-edge semiconductor and SoC designs through comprehensive verification planning, testbench development, and advanced simulation techniques.
Role type
Principal ASIC/SoC Verification Engineer
Builds
Reusable Verification IP (VIP), scalable testbench architectures, and high-quality verification deliverables for SoC/IP designs.
Domain
Semiconductor / SoC Design / Digital Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> production ML models (Note: The text mentions AI/ML techniques applied to verification, but the primary deliverable is verification infrastructure/models for SoC. However, the standard list doesn't fit perfectly. Let's re-evaluate based on the 'Deliverable' options. The role builds verification environments and models. 'product features' is too vague. 'infrastructure' fits the testbench/VIP aspect. 'dashboards & analysis' fits coverage. But the most accurate description of the *output* of a verification engineer is often considered 'product features' (the verified chip) or 'infrastructure' (the verification environment). Given the heavy focus on building testbenches and VIPs, 'infrastructure' is a strong candidate, but the ultimate goal is the chip. Let's look at the options again: production ML models, product features, dashboards & analysis, research, client delivery, infrastructure, physical/clinical work. None fit 'verified SoC' perfectly. 'product features' is the closest if we consider the SoC as the product feature being built. However, the role *builds* the verification environment. Let's select 'infrastructure' as they build the verification infrastructure, or 'product features' as they ensure the product features work. Given the 'Builds' line says 'Reusable VIP... testbench architectures', 'infrastructure' is technically what they build. But the *result* is the chip. Let's stick to the most literal interpretation of what they produce: verification environments and models. 'infrastructure' is the best fit among the limited options for building testbenches/VIPs.
Required skills
SystemVerilog, UVM, constrained-random verification, coverage-driven verification, GLS, timing verification, power-aware verification (UPF/CPF), Python scripting, ARM-based SoC architectures, AMBA protocols, formal verification, CI/regression automation
Preferred skills
AI/ML techniques for verification (intelligent stimulus generation, failure triage), knowledge of EDA tools (Synopsys, Cadence, Siemens)
Technologies
SystemVerilog, UVM, OVM, Python, Perl, Tcl, C/C++, Verilog, UPF, CPF, AXI, AHB, APB, I2C, SPI, UART
Responsibilities
Develop and execute SoC/IP-level verification plans; Architect and enhance SystemVerilog UVM/OVM-based testbenches; Perform Gate-Level Simulation (GLS) and timing verification; Debug complex SoC-level issues involving multiple clock domains and power states; Collaborate with design, architecture, and firmware teams to drive verification closure.
Seniority
Principal, hands-on IC
