Layout Design Manager
Core
Leading a team developing power management ICs for high power density applications, combining people leadership with strong ownership of layout execution.
Role type
Senior IC layout design manager
Builds
Power management ICs (PMICs) for high power density applications
Domain
Semiconductor / Analog Power ICs
Required skills
Analog and power layout techniques, High-voltage design rules, Parasitic-aware layout, Power device layout (LDMOS, MOSFETs), Layout tools (Cadence Virtuoso), Verification flows (DRC, LVS, PEX), Packaging knowledge (bond wire, flip-chip, bump), Team leadership, Cross-functional coordination, Mentoring
Preferred skills
Advanced power packages, Thermal and electrical performance optimization
Technologies
Cadence Virtuoso, DRC, LVS, PEX
Responsibilities
Lead team developing power management ICs, Drive new tools and flows across the team, Manage schedules and resource allocation, Mentor junior layout engineers, Collaborate with circuit designers and foundry partners
Seniority
Senior, hands-on IC
