Design Verification Engineer
Core
Develop and execute verification strategies to ensure first-pass silicon success for next-generation analog and mixed-signal ICs.
Role type
Design Verification Engineer (Analog/Mixed-Signal)
Builds
Verification plans, test benches, simulations, and regression flows for analog power products
Domain
Semiconductor / Analog & Mixed-Signal IC Design
Deliverable
production ML models | product features
Required skills
Analog and mixed-signal (AMS) design verification, SystemVerilog, RTL simulation, regression automation, bug tracking, verification status communication
Preferred skills
Master's degree in EE, analog/digital behavior debug, functional verification methodologies (simulation, assertions, coverage-driven), Real Number models in SystemVerilog EEnet, AI/Machine learning for accelerated DV, scripting (Python, Tcl, Perl)
Technologies
SystemVerilog, Cadence Xcelium, Python, Tcl, Perl
Responsibilities
Develop detailed verification plans with design and system teams; Develop test benches, tests, and simulations using AMS skills; Work with regression tools to submit cases for analysis; Analyze simulation results for compliance; Track and communicate verification status and issues; Contribute to continuous improvements in DV strategy and flows
Seniority
Entry-level to Mid-level, hands-on IC