SRAM Bitcell Engineer

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We are seeking a Senior Device/Circuit Engineer to lead SRAM bitcell development and drive innovation across advanced CMOS technology nodes. The ideal candidate will bring deep expertise in device physics, circuit design, and process technology, combined with proven technical leadership and project management skills. You will spearhead the design and optimization of next-generation SRAM bitcells for implementation across multiple TI product lines.

Key Responsibilities

Technical Leadership:

design, development, and implementation of SRAM bitcells at advanced CMOS nodes

Define and establish bitcell performance specifications and qualification requirements

Lead innovation initiatives in process technology and circuit design to achieve best-in-class memory performance and yield metrics

Conduct detailed technical reviews and provide guidance on design tradeoffs and optimization strategies

Establish design methodologies, standards, and best practices for the team

Project Management

Plan, manage, and oversee project schedules, deliverables, and milestones for multiple concurrent SRAM development projects

Ensure bitcell specifications meet customer requirements, project deadlines, and qualification standards

Identify, assess, and mitigate process and design risks across PVT and manufacturing variations

Drive timely resolution of technical issues and roadblocks

Manage engineering resources and prioritize work across competing objectives

Collaboration and Communication

Partner with SRAM circuit architecture and SoC teams to align memory bitcell goals with system-level requirements

Interface with process technology teams and fab partners to develop and optimize technology to meet specifications

Present strategic project updates, technical reviews, and comprehensive status reports to senior management and stakeholders

Build and maintain strong relationships with internal and external technical teams

Champion cross-functional collaboration and knowledge sharing

Innovation, Mentorship, and Continuous Improvement

Drive a culture of continuous improvement in process development, device optimization, design methodologies, and engineering workflows

Stay at the forefront of industry trends, emerging technologies, and best practices in memory design and process technology

Mentor junior engineers, fostering their technical development and career growth

Lead technology roadmapping and strategic planning for next-generation SRAM solutions

Contribute to technical publications, patents, and industry engagement

Qualifications

Education

Ph.D. in device physics, electrical engineering, semiconductor physics, memory technologies, or related field with 3+ years of experience, OR

Master's degree in related field with 6+ years of industry experience in process development or SRAM design

Experience

6+ years of professional experience in device/circuit design, process technology development, or SRAM bitcell design at advanced nodes

Technical Skills

Expert-level understanding of SRAM bitcell design, performance metrics, and critical tradeoffs

Deep knowledge of scaled MOSFET device physics, including short-channel effects and advanced phenomena

Comprehensive expertise in advanced CMOS process technology development (28nm and below)

Advanced proficiency in simulation tools (Cadence Virtuoso, SPICE, Sentaurus) and device modeling

Strong background in design verification, characterization methodologies, and test development

Leadership and Management Skills

Proven track record of technical leadership on complex, multi-faceted projects

Excellent project management, organizational, and problem-solving skills

Demonstrated ability to mentor and develop engineering teams

Exceptional interpersonal and communication skills (written and verbal)

Desirable

Significant fab experience (process integration, device development, manufacturing) with advanced CMOS technology from development through production

Deep knowledge of reliability challenges at transistor and bitcell level (retention time, soft errors, BTI, hot carrier effects)

Extensive silicon characterization and silicon-to-model correlation experience

Published technical papers or patents in semiconductor device/memory design

Experience with yield analysis and Design-for-Yield (DFY) methodologies

Background in technology road mapping and strategic planning

Experience with advanced process integration challenges at scaled nodes

Strong track record of driving innovation and process/design improvements with measurable impact