SRAM Bitcell Engineer
Core
Lead SRAM bitcell development and drive innovation across advanced CMOS technology nodes for TI product lines.
Role type
Senior Device/Circuit Engineer (SRAM bitcell)
Builds
Next-generation SRAM bitcells for implementation across multiple TI product lines
Domain
Semiconductor manufacturing, advanced CMOS process technology, memory design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SRAM bitcell design, scaled MOSFET device physics, advanced CMOS process technology development, simulation tools (Cadence Virtuoso, SPICE, Sentaurus), design verification, characterization methodologies, test development, technical leadership, project management, mentorship
Preferred skills
Fab experience (process integration, device development, manufacturing), reliability challenges knowledge (retention time, soft errors, BTI, hot carrier effects), silicon characterization, silicon-to-model correlation, yield analysis, Design-for-Yield (DFY) methodologies, technology road mapping, published technical papers or patents
Technologies
Cadence Virtuoso, SPICE, Sentaurus
Responsibilities
Design, development, and implementation of SRAM bitcells at advanced CMOS nodes; Define and establish bitcell performance specifications and qualification requirements; Lead innovation initiatives in process technology and circuit design; Conduct detailed technical reviews and provide guidance on design tradeoffs; Plan, manage, and oversee project schedules for multiple concurrent SRAM development projects; Partner with SRAM circuit architecture and SoC teams to align memory bitcell goals with system-level requirements; Mentor junior engineers and foster their technical development
Seniority
Senior, hands-on IC with technical leadership
