Principal Engineer, SRAM Design
Core
Design, develop, and verify high-performance SRAM and register-file memory IP and testchip content for advanced semiconductor technologies.
Role type
Principal IC analog memory circuit engineer
Builds
Production-ready SRAM macro IP and testchip content for memory and storage solutions
Domain
Semiconductor / VLSI / Memory
Required skills
SRAM and register-file architecture, transistor-level CMOS circuit design, bitcell and peripheral circuit design, PVT corner analysis, Monte Carlo simulation, parasitic-aware post-layout simulation, Python/Tcl/Perl/SKILL automation, testchip planning, foundry collaboration, mentorship
Preferred skills
Low-power SRAM compilers, RTL-to-GDS methodologies, agentic AI for design automation, silicon correlation experience
Technologies
Cadence Virtuoso, Spectre, FineSim, HSPICE, Python, Tcl, Perl, SKILL
Responsibilities
Design and verify memory-array subsystems including bitcells, sense amplifiers, and decoders; Evaluate circuit stability and performance across PVT and aging conditions; Own transistor-level simulation and signoff; Partner with layout and CAD teams on floorplanning and routing; Develop automation for simulation and regression; Plan and support SRAM testchips; Engage with foundry partners on device behavior; Create circuit specifications and design documentation; Mentor engineers on memory-circuit fundamentals
Seniority
Principal, hands-on IC with mentorship
