SRAM Design Lead
Core
Design and optimize high-performance, low-power embedded SRAM and register-file memory IP for advanced semiconductor technologies.
Role type
Senior IC SRAM Design Lead
Builds
Custom SRAM, register-file, and embedded-memory circuits for SoC integration
Domain
Semiconductor / VLSI / Memory Design
Required skills
SRAM and register-file circuit design, bitcell arrays, sense amplifiers, address decoding, control logic, PPA optimization, transistor-level simulation, layout collaboration, memory compilers, testchip development, silicon bring-up, Python/Tcl/Perl/SKILL automation
Preferred skills
Low-power SRAM compilers, bitcell stability analysis, retention modes, RTL-to-GDS methodologies, agentic AI for design automation
Technologies
Cadence Virtuoso, HSPICE, Spectre, FineSim, Python, Tcl, Perl, SKILL
Responsibilities
Design and optimize custom SRAM circuits from architecture through layout support; Develop and verify memory-array subsystems including bitcells, sense amps, and datapaths; Evaluate circuit stability and power across PVT and aging conditions; Own transistor-level simulation and signoff; Drive PPA optimization; Define characterization methodologies; Partner with layout engineers on floorplanning and routing; Support memory-compiler development; Develop automation for simulation and regression; Plan and support SRAM testchips; Lead pre- and post-silicon verification; Create circuit specifications and documentation; Mentor engineers on memory-circuit fundamentals
Seniority
Senior, hands-on IC with mentorship responsibilities
