ASIC DFT Emulation Technical Lead
Core
Architect state-of-the-art emulation environments and lead pre-silicon test plan execution for complex ASICs.
Role type
Senior IC ASIC DFT Emulation Technical Lead
Builds
Pre-silicon emulation platforms and test strategies for Cisco Silicon One networking hardware
Domain
Semiconductor Design / ASIC Development / Hardware Validation
Required skills
ASIC emulation (Palladium, Veloce, Zebu), Verilog, System Verilog, C/C++, Tcl, Python, Perl, scan architecture, MBIST, JTAG
Preferred skills
DFT Emulation strategy definition, UVM, Post Silicon validation, boundary scan
Technologies
Palladium, Veloce, Zebu, UVM, System Verilog
Responsibilities
Architect emulation environments, execute pre-silicon test plans, validate scan/MBIST/JTAG architectures, troubleshoot critical issues, ensure post-silicon pattern conversion
Seniority
Senior, hands-on IC
