ASIC Packaging Signal/Power Integrity Hardware Engineering Technical Lead (Remote)
Core
Lead signal and power integrity (SI/PI) design and verification for next-generation 2.5D/3D ASIC packaging deployed in high-performance switching, routing, and wireless platforms.
Role type
Senior IC ASIC Packaging Technical Lead (Signal/Power Integrity)
Builds
High-volume, high-performance ASIC packages utilizing 2.5D fanout technologies and heterogeneous system integration for Cisco Silicon One architecture.
Domain
Semiconductor hardware engineering, advanced packaging, high-speed digital design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
High-speed architecture & theory (Transmission Line Theory, electromagnetics, S-parameters, impedance analysis), SI/PI simulation (pre/post-layout), layout review & physical validation, SPICE circuit analysis, 56G PAM4 SerDes channel modeling, BER prediction
Preferred skills
High-bandwidth memory (HBM) interface SI, die-to-die interfaces (UCIe), advanced packaging (CoWoS, EMIB, interposer-based designs), Vector Network Analysis, IBIS
Technologies
Cadence Sigrity, Ansys HFSS, Keysight ADS, Cadence APD, Ansys EM flows
Responsibilities
Develop and implement design rules for ultra-high-speed signaling; Analyze substrate SI/PI and collaborate with layout teams; Design and document ASIC packages for high-volume release; Resolve complex technical issues using advanced technology design rules; Define processes and tools for complex ASIC/package development; Mentor junior engineers and influence packaging/hardware teams
Seniority
Senior, hands-on IC with mentorship responsibilities
