ASIC Physical Design Technical Lead
Core
Lead full-chip physical design implementation for AI-era switching, routing, and wireless silicon platforms, optimizing for performance, power, and die size.
Role type
Senior IC ASIC Physical Design Technical Lead
Builds
Full-chip RTL-to-GDSII implementations for Cisco core networking products
Domain
Semiconductor / ASIC Physical Design / AI Infrastructure
Deliverable
production ML models | product features
Required skills
Full-chip floorplanning, hierarchical implementation flow, RTL-to-GDSII flow, static timing analysis, power integrity analysis, physical verification, equivalence checks, low-power design (UPF), EDA tool expertise (Innovus, Tempus/Primetime, Redhawk/Voltus, Calibre/Pegasus), 7nm/5nm/3nm process technology experience
Preferred skills
Hierarchical design convergence, custom clock mesh/H-tree planning, Python scripting for AI tool integration, signoff methodology definition
Technologies
Innovus, Tempus, Primetime, Redhawk, Voltus, Calibre, Pegasus, UPF, 7nm, 5nm, 3nm
Responsibilities
Create full-chip floorplans based on architecture and IP constraints; execute partition, pin assignment, clock plan, and bump planning; perform place and route with timing and power optimization; analyze and enhance tool flows; collaborate with RTL, DFT, and EDA teams; validate signoff methodologies with foundry and IP vendors.
Seniority
Senior, hands-on IC
