ASIC Engineering Physical Design Leader
Core
Lead physical design implementation for silicon photonics driver integrated circuits in advanced CMOS nodes for high-speed optical transceivers (100/200/400G per Lambda).
Role type
Senior IC ASIC Physical Design Lead
Builds
Silicon photonics driver ICs for next-generation optical transceivers and Co-packaged Optics (CPO)
Domain
Semiconductor / Silicon Photonics / Data Center Networking
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RTL-to-GDSII implementation, hierarchical floor planning, place and route, clock tree synthesis, static timing analysis, timing closure, power integrity analysis, IR/EM analysis, physical verification, automation scripting (TCL/Python/Bash/Perl), mixed-signal integration
Preferred skills
High-speed/high-density macro-dominant block design, functional equivalence checking, power grid design optimization, standard-cell IP selection, mixed-signal design integration
Technologies
Tempus, Tempus ECO, Python, Perl, TCL, Shell Scripts, EDA tools
Responsibilities
Own RTL/netlist-to-GDSII implementation for block-level and full-chip designs; develop digital implementation flows and collaborate with EDA vendors; execute hierarchical floor plans and timing closure; run back-end signoff checks including power integrity and physical verification; develop automation scripts for flow efficiency; collaborate with cross-functional teams to resolve design issues.
Seniority
Senior, hands-on IC
