ASIC Engineering Layout Leader | Custom IC layout, Analog, Mixed-signal, and high-speed designs | 12+ years, Bangalore
Core
Lead end-to-end physical implementation of high-performance analog, mixed-signal, and high-speed circuits (SerDes, PAM4) from concept through tapeout for Cisco's next-generation optical interconnect solutions.
Role type
Senior IC layout lead (analog/mixed-signal/high-speed)
Builds
Custom silicon solutions for 100G, 200G, and 400G per lambda optical interconnect technologies
Domain
Semiconductor manufacturing / High-speed optical networking
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Custom IC layout, block-level and top-level floorplanning, placement and routing, physical verification (DRC/LVS/ERC), parasitic-aware design, SerDes/PAM4 interface design, tapeout readiness, cross-functional technical leadership
Preferred skills
Advanced-node layout (FinFET/GAA), layout techniques (common-centroid, interdigitation, shielding), signal/power/thermal integrity analysis, EM/IR analysis, Python/Perl/TCL scripting, Linux environment proficiency
Technologies
Cadence Virtuoso, Linux
Responsibilities
Lead end-to-end layout development for complex analog, mixed-signal, and high-speed circuits; Own block-level and top-level floorplanning, placement, routing, and integration; Translate circuit schematics and performance requirements into optimized, manufacturable layouts; Optimize designs for parasitics, matching, signal integrity, power integrity, thermal behavior, and yield; Ensure compliance with all physical verification requirements; Drive integration across analog, digital, and high-speed domains; Partner with packaging teams on bump planning, pad ring, ESD, and overall package integration; Mentor junior engineers and strengthen layout best practices; Support silicon bring-up, debug, and failure analysis
Seniority
Senior, hands-on IC with leadership responsibilities
