ASIC Design Verification Technical Leader
Core
Lead verification methodology and standards for Cisco's silicon photonics driver integrated circuits (100/200/400G per Lambda) and debug complex silicon/system-level issues during bring-up.
Role type
Senior IC ASIC Design Verification Technical Leader
Builds
High-speed optical transceivers and Co-packaged Optics (CPO) for data center networking
Domain
Silicon Photonics / Optical Networking / ASIC Design
Required skills
System Verilog, UVM, ASIC Design Verification, SoC verification, Team leadership, Scripting (Python/Perl/TCL/Shell), Debugging, SerDes IP, D2D PHY IP, ODSP, Integrated drivers/TIA, Control functions, Formal Verification, HDLs, Emulation/Prototyping platforms
Preferred skills
Scalable/reusable coverage-driven verification environments, Design for testability influence, Troubleshooting expertise, Architecture collaboration
Technologies
System Verilog, UVM, Python, Perl, TCL, Shell Scripts, Veloce, HAPS, Verilog, Ethernet, UCIE, UAL, SPI, I2C
Responsibilities
Define and lead verification methodology and standards across multiple projects; Lead verification at block & chip level with high-speed IPs; Review specifications and influence architecture for testability; Mentor and coach verification engineers; Debug complex silicon and system-level issues; Support post-silicon bring-up and optimize integration and performance
Seniority
Senior, hands-on IC with leadership responsibilities
