ASIC Design Verification Technical Leader
Required skills
Bachelor's degree in Electrical or Computer engineering and 8+ years of ASIC Design Verification experience, or Master's degree in Electrical Engineering or Computer Engineering and 6+ years of ASIC Design experience, or PhD in Electrical Engineering or Computer Engineering + 3 years in ASIC Design Verification experience
Required skills
Experience in System Verilog, UVM, and verification methodologies
Required skills
Experience owning and delivering verification for large-scale SoCs or subsystems
Required skills
Experience leading verification teams or projects
Required skills
Experience in scripting and automation such as Python, Perl, TCL, or Shell Scripts
Preferred skills
Strong experience with UVM (Universal Verification Methodology) for developing scalable, reusable, and coverage-driven verification environments
Preferred skills
Expertise in verification of SerDes IP, D2D PHY IP, ODSP & integrated transceiver features, CPU sub-system & Protocols (Ethernet, UCIE, UAL, SPI/I2C, etc.)
Preferred skills
Experience influencing design for testability and verification
Preferred skills
Proven experience in troubleshooting and debugging
Preferred skills
Experience with Formal Verification, hardware description languages (HDLs) such as Verilog/System Verilog
Preferred skills
Experience with emulation and prototyping platforms (Veloce, HAPS)
Preferred skills
Experience collaborating with architecture and design teams on verification strategy
Responsibilities
Define and lead verification methodology and standards across multiple projects, coordinating activities across multiple sites
Responsibilities
Lead verification at block & chip level with various high-speed IPs integrated like ODSP, D2D IP, SerDes XSR/PAM4, Integrated drivers/TIA, and control functions
Responsibilities
Review specifications, participate in design reviews, and influence architecture for testability and verification efficiency
Responsibilities
Mentor and coach verification engineers, driving continuous improvement in technical skills and execution
Responsibilities
Debug complex silicon and system-level issues during bring-up phases
Responsibilities
Support post-silicon bring-up and optimize integration and performance
Seniority
Technical Leader
Domain
ASIC Design Verification, Silicon Photonics, Optical Transceivers, Data Center Networking
