ASIC Design Verification Technical Leader
Core
Lead verification methodology and standards for Cisco's silicon photonics driver integrated circuits (100/200/400G per Lambda) and high-speed optical transceivers.
Role type
Senior IC ASIC Design Verification Technical Leader
Builds
High-speed optical transceivers, silicon photonic platforms, and Co-packaged Optics (CPO) for data center networking.
Domain
Semiconductor / Silicon Photonics / Data Center Networking
Deliverable
production ML models | product features
Required skills
ASIC Design Verification, System Verilog, UVM, SoC verification, team leadership, scripting (Python/Perl/TCL/Shell), debugging complex silicon issues
Preferred skills
Formal Verification, emulation/prototyping platforms (Veloce, HAPS), SerDes/D2D PHY/ODSP IP verification, design for testability influence
Technologies
System Verilog, UVM, Python, Perl, TCL, Shell Scripts, Verilog, Veloce, HAPS
Responsibilities
Define and lead verification methodology across multiple projects; Lead verification at block & chip level with high-speed IPs; Review specifications and influence architecture for testability; Mentor verification engineers; Debug complex silicon and system-level issues during bring-up; Support post-silicon bring-up and optimize integration
Seniority
Senior, hands-on IC with leadership responsibilities