ASIC Design Engineering Technical Leader
Core
Lead architecture and micro-architecture of high-performance ASIC subsystems for next-generation data center silicon, driving technical execution across design, verification, and physical implementation teams.
Role type
Senior IC ASIC Design Technical Leader
Builds
High-performance silicon for Cisco's core Switching, Routing, and Wireless products
Domain
Data center networking and storage infrastructure
Deliverable
production ML models | product features | infrastructure
Required skills
High-performance RTL design (Verilog/SystemVerilog), timing closure, power optimization, clock gating, ASIC development flows (simulation, synthesis, STA), debug and root-cause analysis, cross-team collaboration, mentorship
Preferred skills
Data center networking/storage architectures (RDMA, NVMe-over-TCP), ARM-based SoC architectures (AXI, CHI, APB, AHB, CMN, GIC, SMMU), high-speed interfaces (PCIe, Ethernet MAC, DDR/LPDDR, DMA), third-party IP integration, engineering automation scripting (Python, Perl, TCL, shell), emulation/prototyping/formal verification
Technologies
Verilog, SystemVerilog, Python, Perl, TCL, shell, PCIe, Ethernet MAC, DDR, LPDDR, DMA, AXI, CHI, APB, AHB, CMN, GIC, SMMU, RDMA, NVMe-over-TCP
Responsibilities
Drive architecture and micro-architecture of high-performance ASIC subsystems; Influence system architecture and key design decisions across complex SoC subsystems; Design and implement high-frequency, high-performance RTL meeting aggressive targets; Lead design specifications and technical reviews; Drive technical execution across architecture, design, verification, and physical implementation teams; Collaborate with verification and physical design teams to close functional coverage, timing, and integration challenges; Mentor engineers and elevate engineering rigor; Lead debug and root-cause analysis across simulation, system bring-up, and post-silicon validation
Seniority
Senior, hands-on IC with mentorship responsibilities
