DFT Intern - ASIC Student - Israel - ETR
Core
Insert DFT logic, perform synthesis, run Automatic Test Pattern Generation (ATPG), execute Gate Level Simulations, timing checks, and DRC checks to ensure hardware testability and design integrity.
Role type
DFT Intern (ASIC)
Builds
Test structures embedded within chips for manufacturing defect detection
Domain
Semiconductor design / ASIC / Digital Logic
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RTL development, synthesis, ATPG, Gate Level Simulation, timing analysis, DRC checks, regression testing, debugging
Preferred skills
Independent learning, interdisciplinary adaptability
Technologies
Synthesis tools, ATPG tools, Simulation environments, DRC checkers
Responsibilities
Insert DFT logic, perform synthesis, run ATPG, execute Gate Level Simulations, perform timing and DRC checks, run regressions, debug simulation failures
Seniority
Intern (Student)
