ASIC Leader
Core
Lead front-end design and verification for Cisco's unified programmable silicon architecture, defining micro-architecture and ensuring verification closure for future routing portfolio devices.
Role type
Senior IC ASIC Design Leader (Front-End)
Builds
Unified programmable silicon architecture for Cisco's future routing portfolio
Domain
Semiconductor / Chip Design / Networking Infrastructure
Deliverable
production ML models | product features | infrastructure
Required skills
Micro-architecture specification, UVM-based verification, functional verification methodologies, bug resolution, coverage closure, post-silicon validation, root-cause analysis
Preferred skills
MATLAB simulations, bit-exact modeling, mixed-signal systems, GLS
Technologies
UVM, MATLAB, GLS
Responsibilities
Review micro-architecture specifications, supervise verification team members, implement Verification environment UVM based, collaborate with Design engineers to resolve bugs, work with firmware/Lab teams to verify chip flows, perform debug and post-silicon validation
Seniority
Senior, hands-on IC with leadership responsibilities
