Early Career - SoC Digital Design Engineer (M, F, D)
Core
Develop RTL for SoC blocks and manage the digital design flow from microarchitecture specification to synthesis.
Role type
SoC Digital Design Engineer
Builds
System-on-Chip (SoC) digital logic blocks for Apple hardware products
Domain
Semiconductor / SoC Design
Required skills
RTL coding, Verilog, System Verilog, block-level simulations, synthesis, Clock/Reset/Voltage domain crossing, DFT, Low Power Design, power optimisation
Preferred skills
Python, Perl, C, C++, TCL, backend tools (synthesis and STA), verification methodologies, microarchitecture definitions
Technologies
Verilog, System Verilog, Python, Perl, C, C++, TCL
Responsibilities
Develop microarchitecture specs with architecture team, Develop RTL for blocks following design guidelines, Implement sophisticated design practices (Clock/Reset/Voltage domain crossing, DFT, Low Power Design), Collaborate with verification team for quality delivery, Optimize design with physical design team for area/timing/power targets
Seniority
Early Career
