IP Logic Design Engineer - Advanced Technologies Group
Core
Develop and implement RTL micro-architecture for next-generation PHY designs, collaborating with architecture, analog, CAD, and timing teams to deliver elite physical layer solutions.
Role type
Senior IC logic design engineer (PHY/ASIC)
Builds
Next-generation PHY designs and SoC blocks
Domain
Semiconductor hardware design (PHY, ASIC, RTL)
Required skills
RTL implementation, Micro-architecture design, System Verilog, Verilog, C/C++, ASIC verification flows, STA methodology, Perl/Tcl scripting, PHY design standards, GDS implementation, Frontend simulators/debuggers
Preferred skills
AMS PHY experience, Design methodology for correct-by-construction designs, Debugging PHY-level issues
