ASIC Design Engineering Technical Leader
Core
Lead ASIC front-end design for Cisco Silicon One routing portfolio, covering micro-architecture, RTL implementation, and full-chip integration.
Role type
Senior IC ASIC Design Engineering Technical Leader
Builds
High-performance silicon chips for Cisco's future routing portfolio
Domain
Semiconductor / Network Infrastructure / ASIC Design
Deliverable
production ML models
Required skills
micro-architecture specification, RTL design (Verilog/SystemVerilog), timing analysis, chip integration, debug and root-cause analysis, post-silicon validation
Preferred skills
MATLAB simulations, bit-exact modeling, mixed-signal systems, Clock Domain Crossing (CDC)
Technologies
Verilog, SystemVerilog, UVM, MATLAB
Responsibilities
Write and review micro-architecture specifications, implement RTL to meet timing/performance/power, contribute to full chip integration, collaborate with verification on bug resolution, work with physical design on PnR issues, perform lab debug and validation
Seniority
Senior, hands-on IC with technical leadership
