CAD Engineer – EMIR Signoff
Core
Ensure verification and analysis work is completed on complex mixed-signal designs prior to tapeout, applying hands-on experience in power/EMIR analysis to develop and refine signoff methodologies.
Role type
Senior IC signoff engineer (mixed-signal/SoC)
Builds
High-performance, power-efficient system-on-chip (SoC) processors for Apple
Domain
Semiconductor design, mixed-signal circuits, EDA
Deliverable
production ML models
Required skills
EMIR analysis, mixed-signal design, EDA flows, scripting (Perl/Python), static/dynamic IR analysis, scan-mode IVD analysis, power EM analysis, signal EM, package model handling, IP reuse
Preferred skills
AI/ML and LLM-driven techniques for EDA automation, Redhawk, Voltus, Totem, CMOS analog design, simulation and power analysis
Technologies
Redhawk, Voltus, Totem, Perl, Python
Responsibilities
Define signoff requirements early in the project lifecycle, partner with Design/CAD/Technology teams to confirm EDA flows, interface with design groups for enablement and debug requests
Seniority
Senior, hands-on IC
