ASIC Design Verification Technical Leader
Core
Lead ASIC design verification by driving test planning and developing advanced test benches to ensure design integrity for cutting-edge hardware solutions.
Role type
Senior IC ASIC Design Verification Technical Leader
Builds
Robust test infrastructure and verification solutions for Cisco hardware products
Domain
Semiconductor / ASIC Design / Hardware Verification
Required skills
System Verilog, testbench development, Tcl/Python/Perl scripting, DVE/Verdi debugging, constrained-random verification, functional coverage, ASIC design flow knowledge (via careerplan.io/jobs/2006869-asic-design-verification-technical-leader-at-cisco)
Preferred skills
UVM, JTAG protocol, SLM IP verification strategies
Technologies
System Verilog, Tcl, Python, Perl, DVE, Verdi, UVM, JTAG
Responsibilities
Drive comprehensive test planning, develop advanced test benches, integrate and validate test logic, utilize scripting and debugging tools to streamline workflows, optimize test processes
Seniority
Senior, hands-on IC
