ASIC Engineering Technical Leader
Core
Lead ASIC digital design and physical design methodologies for advanced silicon architecture in networking chips.
Role type
Senior IC ASIC Engineering Technical Leader
Builds
Next-generation silicon architecture for advanced global networks
Domain
Semiconductor / Networking / ASIC Design
Deliverable
production ML models | product features
Required skills
ASIC digital design, Verilog/System Verilog, RTL design, micro-architecture, SoC integration, verification, front-end tools (simulation, linting, CDC, synthesis, formal verification), interface protocols (AMBA, JTAG), Python/Tcl/Make scripting (via careerplan.io/jobs/2006866-asic-engineering-technical-leader-at-cisco)
Preferred skills
Sensors IP development, power optimization (UPF), DFT/MBIST
Technologies
Verilog, System Verilog, Python, Tcl, Make, AMBA, AXI, APB, AHB, JTAG
Responsibilities
Define innovative Physical Design methodologies, create robust flows for complex chip development, mentor engineers, drive next-generation silicon architecture development, collaborate on sub-system/SoC integration and verification, resolve complex verification failures, interact with physical design team to improve QoR
Seniority
Senior, hands-on IC with leadership responsibilities
