Analog Design and Verification Flow (M/F/D)
Core
Develop an agentic flow to automate the correlation of specs and simulation data against ATE and lab test results for analog circuits.
Role type
Senior IC analog design verification flow engineer
Builds
Automated verification flows linking Cadence Virtuoso design environments to downstream verification data
Domain
Analog IC design and verification
Required skills
Analog circuit design fundamentals, Cadence Virtuoso, Python, Perl, SKILL, agentic flows, simulation setup, ATE correlation, report generation
Preferred skills
Master's degree in Electrical Engineering or Computer Science
Technologies
Cadence Virtuoso, Python, Perl, SKILL, ATE
Responsibilities
Apply spec-driven custom design methodology from specification capture through simulation setup and results checking, Develop automation that links design and simulation environments to downstream verification data, Create agentic flows that pull, align, and compare specs and simulation results with ATE and bench/lab measurements, Define and generate correlation reports and dashboards, Work with analog designers, test engineers, and CAD/methodology teams across multiple sites, Document the flow and support its adoption by circuit design teams