ASIC Design Engineer — Pixel IP
Core
Design high-performance, low-power pixel processing engines and digital signal processing pipelines for capturing, improving, compressing, and displaying digital still images and video.
Role type
Senior IC ASIC Design Engineer (Pixel IP)
Builds
Next-generation, high-performance, power-efficient system-on-chips (SoCs) for Apple devices
Domain
Consumer electronics / Digital Signal Processing / SoC Design
Required skills
RTL design (Verilog/System Verilog), Micro-architectural specification, Low-power design techniques, Cross-functional collaboration, Synthesis and optimization, Digital hardware design
Preferred skills
Media/video/pixel/display design experience, On-chip bus protocols (AMBA/AXI/AHB/APB), Front-end implementation (synthesis/timing/power analysis), Scripting (Python/Perl/TCL)
Technologies
Verilog, System Verilog, Python, Perl, TCL, AMBA, AXI, AHB, APB
Responsibilities
Design digital hardware using RTL or high-level synthesis with embedded assertions and cover points; Write detailed micro-architectural specifications; Collaborate with cross-functional teams to maximize performance while minimizing power and area; Synthesize designs and optimize for power, timing, and area; Work with verification teams to debug and verify functionality and performance; Manage deliverables to align with project goals
Seniority
Senior, hands-on IC
