PHY RTL Design Engineer
Core
Develop signal processing intensive RTL designs for wireless communication SoCs, focusing on energy efficiency, low latency, and scalability.
Role type
Senior IC RTL Design Engineer (Wireless PHY)
Builds
Wireless SoCs for consumer electronics
Domain
Semiconductor / Wireless Communications
Deliverable
production ML models | product features
Required skills
RTL Design, Digital Communications, DSP fundamentals, Microarchitecture definition, Power/Area optimization, Synthesis, Timing constraints, Lint/CDC/RDC verification
Preferred skills
UVM DV environment, Fixed-point arithmetic, Bit-true cycle-accurate verification, Wireless protocols (Viterbi, LDPC, Polar, Filter design), IEEE 802.11/802.15/Bluetooth/3GPP standards, Bus fabric (APB/AHB/AXI), Power management, FPGA/emulation platforms
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