PHY RTL Design Engineer
Core
Develop signal processing intensive RTL designs for wireless communication SoCs, focusing on energy efficiency, low latency, and scalability.
Role type
Senior IC RTL Design Engineer (Wireless PHY)
Builds
Wireless SoCs for consumer electronics
Domain
Semiconductor / Wireless Communications
Deliverable
production ML models | product features
Required skills
RTL Design, Digital Communications, DSP fundamentals, Microarchitecture definition, Power/Area optimization, Synthesis, Timing constraints
Preferred skills
UVM DV, Fixed-point arithmetic, Bit-true cycle-accurate verification, Wireless protocols (802.11, 802.15, Bluetooth, 3GPP), Filter design, Bus fabric (APB/AHB/AXI), FPGA/emulation
Technologies
MATLAB/C, RTL, UVM, IEEE 802.11, 802.15, Bluetooth, 3GPP, APB, AHB, AXI
Responsibilities
Write specifications and define microarchitecture based on system models; Architect area and power-efficient designs; Perform RTL coding and verification for PHY modem development; Support backend activities and silicon bringup.
Seniority
Senior, hands-on IC
