SoC Physical Design Engineer, PnR
Core
Physical implementation of design partitions from netlist to tapeout for highly complex SoCs.
Role type
Senior IC SoC Physical Design Engineer (PnR)
Builds
SoC chips for Apple hardware products
Domain
Semiconductor / SoC Physical Design
Required skills
netlist to GDS2 implementation, timing closure, physical verification, electrical verification, floorplanning, clock and power distribution, large SoC design experience (>20M gates), sub-10nm process node experience, industry standard EDA tools
Preferred skills
partition-level P&R methodology, physical design flow construction and analysis, strict schedule and die size optimization
Responsibilities
Collaborate with logic design teams on partition architecture, complete netlist-to-GDS2 implementation, perform timing/physical/electrical verification, resolve physical design flow issues
Seniority
Senior, hands-on IC