SoC Physical Design Engineer, PnR
Core
Physical implementation of design partitions from netlist to tapeout for highly complex SoCs.
Role type
Senior IC SoC Physical Design Engineer (PnR)
Builds
SoC chips for Apple hardware products
Domain
Semiconductor / SoC Physical Design
Required skills
floorplanning, clock and power distribution, timing closure, physical and electrical verification, PnR optimization, large SoC design experience (>20M gates), multi-vt strategies, mixed signal block integration, industry standard tools
Preferred skills
MS in Electrical/Electronics/Computer Engineering, Design for Yield and Manufacturability, global timing verification, physical design verification flows, adherence to stringent schedule and die size requirements
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