SoC Physical Design Engineer, PnR
Core
Physical implementation of design partitions from netlist to tapeout for highly complex SoCs.
Role type
Senior IC SoC Physical Design Engineer (PnR)
Builds
SoC chips for Apple hardware products
Domain
Semiconductor / SoC Physical Design
Required skills
netlist to GDS2 implementation, timing closure, physical and electrical verification, PnR optimization, floorplanning, clock and power distribution, multi-vt strategies, mixed signal block integration, industry standard tools, large scale SoC design (>20M gates)
Preferred skills
MS in Electrical/Electronics/Computer Engineering, Design for Yield and Manufacturability, global timing verification, physical design verification flows
Technologies
P&R flows, floorplanning tools, global timing verification tools, physical design verification flows
Responsibilities
Work with logic design team to understand partition architecture and drive physical aspects early, Complete netlist to GDS2 implementation meeting schedule and design goals, Perform timing, physical and electrical verification and drive signoff closure, Resolve and improve design and flow issues related to physical design, Drive optimization of PnR partitions for Power/Performance/Area
Seniority
Senior, hands-on IC