ASIC Design Engineer - Cache Controller
Core
Design and develop hardware for cache subsystems in high-performance System on a Chip (SoC) to address real-time, low latency, and high-bandwidth challenges.
Role type
Senior IC ASIC Design Engineer (Cache Controller)
Builds
Special purpose cache and controller components for mobile SoC memory hierarchy
Domain
Semiconductor / Hardware Design / Mobile Computing
Required skills
ASIC design, RTL design, micro-architecture definition, PPA analysis, memory system development, netlist generation, timing analysis
Preferred skills
Cache design, multi-processor cache coherence protocols, high-performance coherent memory systems, interconnect architectures, high-performance DRAM controller
Technologies
RTL, SoC, Cache, Memory Subsystems, PPA, Netlist
Responsibilities
Develop cache micro-architecture based on guidelines and model analysis, explore architecture trade-offs in performance/area/power, debug RTL design of cache sections, work on front-end netlist and area/timing analysis, collaborate with physical design team on timing closure
Seniority
Mid-Senior, hands-on IC
