SoC Power Flow Methodology Engineer
Core
Develop and enhance automated low-power design and verification flows for next-generation chip architecture.
Role type
Senior IC power flow methodology engineer
Builds
Automated flows and tools for power analysis, optimization, and verification
Domain
Semiconductor / VLSI / Low-power chip design
Required skills
VLSI design flows, scripting (Python/C++/Java), flow development, object-oriented algorithm design, modern software testing practices, RTL construction/verification, synthesis, P&R
Preferred skills
Tcl/Perl, EDA tools, GUI development, UPF, low-power design concepts
Technologies
Python, C++, Java, Tcl, Perl, EDA tools, UPF
Responsibilities
Create flows and tools for power analysis, optimization, and verification; communicate with design teams to resolve power-related issues; craft low-power methodologies across future technologies
Seniority
Senior, hands-on IC
