Emulation Verification Engineer
Core
Porting large SoC designs onto emulation platforms and executing detailed test plans to verify chip functionality.
Role type
Senior IC emulation verification engineer
Builds
Verified large System-on-Chip (SoC) designs on emulation platforms
Domain
Semiconductor hardware design and verification
Required skills
SoC design verification, emulation platform setup, synthesizable monitor/checker development, test plan creation, low power testing, Verilog/SystemVerilog coding, UVM environment development, random stimulus infrastructure, scripting (Perl/Python/TCL), firmware debugging
Preferred skills
RTL-to-emulation tool flow knowledge, familiarity with Standard Emulators (Palladium, Veloce, Zebu) or FPGA flows, SystemVerilog assertions, C/C++ DPI, UVM acceleration experience
Technologies
Palladium, Veloce, Zebu, Xilinx, Altera, Verilog, SystemVerilog, UVM, C, C++, Perl, Python, TCL
